Regarding methods for raising the operating speed of semiconductor integrated circuits, there are many options, for example by devising ways of implementing a circuit, by changing circuit architecture, etc., Any of the methods address the most fundamental issue of improving transistor operating speeds. By doing so, the speed of any kind of circuit may be improved.
Raising the transistor power supply voltage, or lowering the transistor threshold voltage are both known methods for improving the operating speed of transistors. For example, Non-Patent Literature 1 describes formulae which show the rise time and fall time of a signal outputted by a CMOS integrated circuit. As is made evident by these formulae, transistors operate faster when their power supply voltages are higher or their threshold voltages are lower.
The method disclosed in Patent Literature 1 is a known example among methods for controlling transistor operating speeds by adjusting transistor power supply voltages. With this method, power supply voltages are adjusted individually for combined circuits separated by a plurality of flip-flops. Especially in a combined circuit which includes a critical path, the power supply voltage of every logic element is kept high. Due to this, the operation speed of the combined circuit increases. Here, “critical path” refers to a pathway in a circuit that needs the most amount of time to transmit a signal, or to an important pathway that must absolutely transmit a signal within a provided time. In the method described in Patent Literature 1, a power supply system is established individually for each combined circuit, and therefore the number of power supply systems is great. However, since it is possible to regulate a power supply voltage individually in each combined circuit, power supply voltages can be kept low for combined circuits with a small number of logic stages and lenient speed restrictions. As a result, not only the operating speed of a combined circuit which includes a critical path can be kept at a high level, but also the electric power consumption of the entire circuit can be suppressed.
DVFS (Dynamic Voltage and Frequency Scaling) and AVS (Adaptive Voltage Scaling) are other known technologies. With these technologies, the power supply voltage of a circuit is dynamically adjusted in keeping with operating frequency fluctuations. Specifically, when slow circuit operations are acceptable, the operating frequency is kept at a usual level, and accordingly, the power supply voltage also is kept at a usual level. Alternatively, when fast circuit operations are necessary, the operating frequency is set higher than the usual level, and accordingly, the power supply voltage is adjusted higher than the usual level. In this way, these technologies achieve both an improvement in operating speeds and a reduction in electric power consumption.
The method disclosed in Patent Literature 2 is a known example of a method for controlling transistor operating speeds by adjusting transistor threshold voltages. With this method, transistor threshold voltages are adjusted by heating transistors. Specifically, a heater is provided next to an analog circuit such as a differential amplifier, and the amount of heat produced by the heater is adjusted in accordance with the environmental temperature. Here, when the temperature of a transistor is higher, the threshold voltage of the transistor is lower. When the environmental temperature falls, the heater heats the analog circuit to prevent transistors included in the analog circuit from cooling down. By doing so, the threshold voltages of the transistors are kept low, and their operation speeds kept high. In this way, even at low temperatures, the analog circuit operates stably. Changing the bias voltage of a transistor is another known method for controlling transistor operating speeds by adjusting transistor threshold voltages.
Furthermore, known technology exists for a design to lower the threshold voltages of those transistors which are desired to have high operating speeds. For example, in the semiconductor integrated circuit layout design method disclosed in Patent Literature 3, a library (Hvt Cell Library) made up of transistors with high threshold voltages (Hvt cell), and a library (Lvt Cell Library) made up of transistors with low threshold voltages (Lvt cell) are used together. Specifically, first a netlist which uses only the Lvt cell library is created, or a netlist having a portion thereof forcibly replaced with the Hvt cell library is created. Next, layout data is created in accordance with the netlist. Delay time is then calculated for every pathway included in the layout data. If timing errors are detected in the results of the calculation, then cell resizing, buffer insertion, or cell replacement is performed, after which the delay time of each pathway is calculated again. This operation is repeated until no more timing errors are detected. As a result, transistors placed on a critical path will be made of Lvt cells, and all other transistors will be made of Hvt cells. In other words, transistors that ought to operate at high speeds will have low threshold voltages despite electric power consumptions being high, and transistors which may acceptably run at slow speeds will have low electric power consumptions despite the threshold voltages being high. In this way, with the electric power consumption of the entire circuit being kept low, the transistors placed on the critical path will run at high speeds.